1. Field of the Invention
The present invention relates to an electronic storage device and the control method thereof, more particularly to a non-volatile electronic storage device and the control method thereof.
2. Description of Related Art
NAND-type flash memory is widely used in consuming products to be served as storage media because of rapid access speed and high reliability. Conventional data storage devices are Solid-Stage Drive (SSD), USB Flash Drive (UFD), memory cards etc. In particular, NAND-Type Flash Memory is mainly served as storage media. With the rapid improvement achieved in semi-conductor process, the memory density of the flash memory becomes higher and higher, bytes capable of being stored in a memory cell become more and more, thus causing the data storage capacity of the flash memory becoming bigger and bigger. However, with the enlargement of the capacity of the flash memory, the content of data in each management unit also becomes different.
Conventional capacity of each memory unit page of a flash memory is 2 KB (Byte) plus redundancy bits, as shown in FIGS. 1A and 1B. In FIG. 1A, the memory page contains four 512-byte memory segments S0, S1, S2, and S3, with data D0, D1, D2, and D3 respectively stored in the memory segments S0, 51, S2 and S3. Error Correcting Codes (ECC) E0, E1, E2, and E3 generated according to the data D0, D1, D2 and D3 are respectively stored in the redundancy bits. In FIG. 1B, the memory page also contains four 512-byte memory segments S0, S1, S2 and S3 with data D0, D1, D2 and D3 respectively stored therein. Error Correcting Codes (ECC) E0, E1, E2 and E3 generated according to the data D0, D1, D2 and D3 are respectively recorded after corresponding memory segments S0, S1, S2 and S3.
When accessing data, such as accessing data D0, then the ECC E0 also should be accessed for error detection and correction to the data D0 to assure the right data access. For the same theory, the access to D1, D2 and D3 also should read E1, E2, and E3 for error detection and correction to error bits, thus, assuring the right data access. That means that utilizing E0, E1, E2, and E3 to assure the right access of D0, D1, D2 and D3.
Please refer to FIG. 2, the capacity of a memory page of a large-capacity flash memory is 4 KB plus redundancy bits. Each memory segment S0, S1, S2 or S3 contains 1024 bytes, that is double as 512 bytes. Each 1024-byte memory segment provides several bits of ECC for error detection and correction to the data. In FIG. 2, the data in memory segment S0 is D0 and D1 which is protected by an ECC E01. Data in memory segment S1 is D2 and D3 which is protected by an ECC E23.
However, the capacity of each memory segment of a conventional host system is still 512 bytes, not like 1024 bytes defined by a large-capacity flash memory. Therefore, when the conventional host system requests accessing 512-byte data from a large-capacity flash memory, a controller of the flash memory still needs to read out 1024 bytes and related ECC codes from the flash memory for checking error in the 1024 bytes. If there is an error, the error will be corrected and the correct requested 512-byte data will be accessed.
For example, in FIG. 2, when the host system requests accessing data D0, data in memory segment S0 (D0+D1) and the ECC code E01 generated by D0 and D1 will be all read out, that means that data D0 cannot be accessed directly. So, the additional action of reading the whole memory segment S0 and the related E01 lengthens the error detection and correction time, thus, influencing the data process efficiency of the flash memory.